Image display apparatus using pixel display elements that are driven under current control, such as organic EL displays or the like, have drive circuits associated with respective pixels of driving those pixel display elements, i.e., current control elements. The drive circuits are arrayed two-dimensionally in association with the respective pixels, making up the image display apparatus. In each of the drive circuits, gradation pixel data is written from a signal line through a selection transistor into a holding capacitor which is connected between the gate and source of a drive transistor. The pixel data is held in the holding capacitor during a display period. A signal charge corresponding to the display luminance of the pixel is written in the holding capacitor, and a current depending on the signal charge is supplied from the drive transistor to the pixel display element.
Heretofore, an image display apparatus of the type described above comprises, as shown in FIG. 1, display panel 10, control circuit 20, signal line driver 30, and scanning line driver 40. Display panel 10 comprises an organic EL display, for example, and has a plurality of signal lines X1, . . . , Xi, . . . , Xn to which gradation pixel data D are applied, a plurality of scanning line Y1, . . . , Yj, . . . , Ym to which scanning signals V are applied, and a plurality of pixels 10ij (i=1, 2, . . . , n, j=1, 2, . . . , m) disposed at points of intersection between signal lines X1, . . . , Xi, . . . Xn and scanning line Y1, . . . , Yj, . . . , Ym. Of pixels 10ij, those pixels on scanning lines that are selected by scanning signals V are supplied with gradation pixel data D to display an image.
Control circuit 20 supplies image input signal VD supplied from an external source to signal line driver 30 and also supplies vertical scanning signal PV to scanning line driver 40. Signal line driver 30 applies gradation pixel data D depending on image input signal VD to signal lines X1, . . . , Xi, . . . Xn. Scanning line driver 40 successively generates scanning signals V in synchronism with vertical scanning signal PV supplied from control circuit 2, and applies scanning signals V successively to corresponding scanning line Y1, . . . , Yj, . . . , Ym of display panel 10.
FIG. 2 is a circuit diagram showing an electric arrangement of pixel 10i,j (e.g., i=3, j=2) in FIG. 1.
Pixel 103,2 comprises power line 11, ground line 12, selection transistor 133,2 in the form of an n-channel MOS field-effect transistor (FET) (hereinafter referred to as “nMOS”), holding capacitor 143,2, drive transistor 153,2 in the form of a p-channel MOSFET (hereinafter referred to as “pMOS”), pixel display element 163,2 as a current control element, and parasitic capacitor 173,2. Other pixel 10i,j, such as pixels 104,2, 105,2 (not shown), that are positioned adjacent to pixel 103,2 are of the same structure. Selection transistor 133,2, holding capacitor 143,2, drive transistor 153,2, pixel display element 163,2, and parasitic capacitor 173,2 make up a drive circuit. The pixel display element should preferably comprise an organic EL element, for example.
Selection transistor 133,2 has a gate electrode connected to a selection line (not shown), a drain electrode to signal line X3, and a source electrode to the gate electrode of drive transistor 153,2. Holding capacitor 143,2 is connected between the gate electrode of drive transistor 153,2 and power line 11. Drive transistor 153,2 has its gate electrode connected to the source electrode of selection transistor 133,2 and one end of holding capacitor 143,2, a source electrode connected to power line 11, and a drain electrode to the anode of pixel display element 163,2. Pixel display element 163,2 is connected between the drain electrode of drive transistor 153,2 and ground line 12, and emits light at a luminance depending on current IL3,2 from drive transistor 153,2. Parasitic capacitor 173,2 comprises a parasitic capacitor across pixel display element 163,2.
In pixel 103,2, during a selection period, i.e., when scanning signal V is applied to scanning line Y2, selection transistor 133,2 is turned on, applying gradation pixel data D applied to signal line X3 between the gate and source of drive transistor 153,2. At this time, holding capacitor 143,2 is charged. Then, when the selection period changes to a non-selection period, selection transistor 133,2 is turned off. Since the gate-to-source voltage VGS of drive transistor 153,2 is held by holding capacitor 143,2, current IL3,2 depending on written gradation pixel data D remains to be continuously supplied from drive transistor 153,2 to pixel display element 163,2 during the non-selection period. Pixel 104,2, 105,2 and the like that are positioned adjacent to pixel 103,2 operate in the same manner.
The above conventional image display apparatus has suffered the following problems:
As shown in FIG. 3, drive transistor 153,2 of pixel 103,2, drive transistor 154,2 of pixel 104,2, and drive transistor 155,2 of pixel 105,2 have their respective VGS-IDS (gate-to-source voltage vs. drain-to-source current) characteristics that vary from pMOS to pMOS. In particular, their threshold values widely vary from each other such that even when identical gradation pixel data D are applied between the gates and sources of drive transistors 153,2, 154,2, 155,2, they have different drain-to-source currents IDS IL3,2, IL4,2, IL5,2. Therefore, since different current flow respectively through pixel display element 163,2 of pixel 103,2, pixel display element 164,2 of pixel 104,2, and pixel display element 165,2 of pixel 105,2, pixel display elements 163,2, 164,2, 165,2 emit light at different luminances. During the non-selection period, since the gate-to-source voltages VGS of those drive transistors are held by the corresponding holding capacitors, even though gradation pixel data D are identical, different currents based on the variations of the drive transistors are caused to continuously flow to the current control elements by the drive circuits.
As described above, the conventional image display apparatus is problematic in that even when identical gradation pixel data, i.e., signal voltages, are written, the current control elements emit light at different luminances, lowering the quality of the displayed image.
R. Dawson, et al. have proposed a drive circuit, to be described below, for preventing drive current variations from occurring due to threshold value variations of drive transistors (R. Dawson, et al., “A Poly-Si Active-Matrix OLED Display with Integrated Drivers,” SID' 99 DIGEST, pp. 11-14).
FIG. 4 shows an arrangement of a drive circuit for a current control element proposed by R. Dawson, et al. As shown in FIG. 4, the drive circuit for the current control element comprises selection transistor 24A, holding capacitor 25, drive transistor 26, current control element 27, parasitic capacitor 28, decoupling capacitor 29, and switching transistors 31, 32, which are connected between power line 21, ground line 22, and signal line 23.
Selection transistor 14A comprises a pMOS and has a gate electrode connected to a selection line (not shown), a source electrode to signal line 23, and a drain electrode to one end of decoupling capacitor 29. Holding capacitor 25 is connected between the gate electrode of drive transistor 26 and power line 21. Drive transistor 26 comprises pMOS and has its gate electrode connected to the other end of decoupling capacitor 29 and one end of holding capacitor 15, a source electrode to power line 11, and a drain electrode to the source electrode of switching transistor 32.
Current control element 27 is connected between the drain electrode of switching transistor 32 and ground line 22, and emits light at a luminance depending on a current from drive transistor 26. Parasitic capacitor 28 comprises a parasitic capacitor across current control element 27. Decoupling capacitor 29 is connected between the drain electrode of selection transistor 24A and the gate electrode of drive transistor 26, and isolates selection transistor 24A and drive transistor 26 from each other in terms of direct currents. Switching transistor 31 comprises pMOS and has a gate electrode connected to a resetting line (not shown), a source electrode to the gate electrode of drive transistor 26, and a drain electrode to the drain electrode of drive transistor 26. Switching transistor 32 comprises pMOS and has a gate electrode connected to the resetting line, a source electrode to the drain electrode of drive transistor 26, and a drain electrode to one end of current control element 27.
FIG. 5 is a timing chart illustrative of the manner in which the drive circuit of the conventional current control element shown in FIG. 4 operates. Operation of the drive circuit of the conventional current control element shown in FIG. 4 will be described below.
Before a selection period starts, the drive circuit shown in FIG. 4 is required to discharge parasitic capacitor 28 of current control element 27 to set drain voltage VD of drive transistor 26 to the ground line potential. The voltage of signal line 23 is set to voltage VDD of power line 21.
When the selection period starts, a row selection signal is given to the selection line to turn on selection transistor 24A, and a resetting signal is given from a resetting driver (not shown) to the resetting line to turn on switching transistor 31 and turn off switching transistor 32. The gate and drain electrodes of drive transistor 26 are electrically connected to each other, starting to discharge holding capacitor 25. When a sufficient time elapses, gate voltage VG of drive transistor 26 drops to threshold value VT. Thereafter, switching transistor 31 is turned off, floating the gate electrode of drive transistor 26.
Then, when the input voltage from signal line 23 switches from voltage VDD of power line 21 to write voltage VDATA, gate-to-drain voltage VGS of drive transistor 26 is determined by a capacitance division between capacitance value CD of decoupling capacitor 29 and capacitance value CS of holding capacitor 25, according to the following equation:
                                                        VGS              =                              VG                -                VDD                                                                                        =                              VT                +                                  CD                  ·                                                            (                                              VDATA                        -                        VDD                                            )                                        /                                          (                                              CS                        +                        CD                                            )                                                                                                                              (        1        )            
However, the drain-to-source current of a transistor is generally expressed by a function of (VGS−VT). Since (VGS−VT) is determined by VCATA as can be seen from the above equation, a variation of the threshold value of drive transistor 26 is corrected.
The circuit shown in FIG. 4 requires four transistor for one pixel and also requires a decoupling capacitor in addition to a holding capacitor. Therefore, the aperture of the pixel is reduced, resulting in manufacturing process difficulty. If the value of decoupling capacitance CD is small, then write voltage VDATA needs to be increased, and it is desirable to achieve the relationship. CD>CS. To meet such a demand, a chip area for forming decoupling capacitance CD is increased. Another shortcoming is that it takes time to discharge the parasitic capacitor of the current control element prior to the selection period, and it needs a complex operation to discharge the parasitic capacitor.